SNES Enhanced Cart Support (FW v0.22)

[skaman]

BETA testing of the SNES Enhanced code has been successful with the help of a solid group of testers.

I'll be finalizing the firmware and posting final versions for public download.

Many thanks to all of the testers!

[skaman]

If anyone is interested in a prototype Enhanced Cart Adapter, then PM me for the details.  I have an adapter complete with cutdown Japanese SGB shell available.  I ran out of US SGB shells (like the one pictured) so I only have Japanese SGB shells left.

Thanks!

[danyetman]

If anyone is interested in a prototype Enhanced Cart Adapter, then PM me for the details.  I have an adapter complete with cutdown Japanese SGB shell available.  I ran out of US SGB shells (like the one pictured) so I only have Japanese SGB shells left.

Thanks!

And for my first official post in this forum...Consider yourself PM'd!

[skaman]

I modified the Enhanced Cart Adapter PCB layout.  The new PCB uses only the center 46 pins and places all of the components on one side as suggested by Matthias.  Functionality in the Retrode is the same as the original layout.  The new PCB fits into a standard SFC/SNES shell.

Here are pictures of the new PCB and an assembled adapter:

[Knight of Time]

I'm glad to see you posted an updated version of the Enhanced Cart Adapter skaman (and BTW, congrats on being modded, that was a big surprise, and I'd say you definitely deserve it).

Though, I'm curious to ask if you got any closer to finding a way to make it and the Retrode2 able to backup/restore saves for SA-1 SNES games?  If you haven't, it's not a big deal right now.

[skaman]

I have an idea on implementing the SA-1 SRAM Writes but I haven't been able to implement it.  It will probably take a microcontroller or a bunch of gates.  The CPU CLK needs to be on for BW-RAM (SRAM) Writes but it cannot be on all the time as it corrupts normal reads.  My thought is to toggle the CPU CLK on writes to 0x2200.   On the first write to 0x2200, the CPU CLK will turn on allowing the writes to the SA-1 registers and BW-RAM (SRAM).  On the subsequent write to 0x2200, the CPU CLK will turn off allowing normal reads.

I'll get back to working on the design after the current firmware developments are complete.